The present invention relates to a semiconductor memory device that requires stored data to undergo a storage holding operation, and more particularly, to an internal power supply circuit of a semiconductor memory device that performs low voltage operations.
The power supply voltage of a semiconductor device is being reduced in recent portable electronic equipment, which use a battery as a power source, to increase usage time. The number of semiconductor memory devices operated by a power supply voltage of 2.5V during normal operations has been increasing.
In a semiconductor memory device that is driven by a low voltage, stored data undergoes a storage holding (refresh) operation with a power supply voltage that is lower than 2.5V, for example 1.5V.
FIG. 1 schematically shows a first prior art example of a DRAM internal power supply generation circuit 50. Japanese Unexamined Patent Publication No. 11-86544 describes the power supply generation circuit 50.
The voltage of an external power supply Vccex is 2.5V during a normal operation mode and 1.5V during a self-refresh mode.
In the normal operation mode, a differential amplifier 2 generates a transistor drive signal based on the comparison between a reference voltage Vref generated by a reference voltage generation circuit 1 and an internal circuit voltage Vccin. The transistor drive signal activates a p-channel MOS transistor Tr1. The channel resistance of the transistor Tr1 decreases the voltage of the external power supply Vccex. The external power supply Vccex (internal circuit voltage Vccin), the voltage of which has been decreased, supplies an internal circuit 3 with power.
When a self-refresh detection circuit 4 detects a self-refresh mode based on control signals /RAS, /CAS (/represents a low level, active signal), the self-refresh detection circuit 4 generates a detection signal LLD at a high level. This activates a p-channel MOS transistor Tr2 and supplies the internal circuit 3 with power from the external power supply Vccex, which has 1.5V.
During the self-refresh mode in the first prior art example, when the internal circuit 3 is supplied with power having low voltage (1.5V) from the external power supply Vccex, the refresh operation reduces the voltage of the internal circuit voltage Vccin. This may result in erroneous refreshing.
During the self-refresh mode, the transistor Tr2 is constantly activated but the transistor Tr1 is activated only when the voltage of the internal circuit voltage Vccin is lower than the reference voltage Vref.
FIG. 2 is a circuit diagram of the differential amplifier 2. The voltage of the external power supply Vccex provided to the differential amplifier 2 is 2.5V, the threshold value of a p-channel MOS transistor is 0.9V, and the threshold value of an n-channel MOS transistor is 0.5V. In this case, an n-channel MOS transistor Tr9, which is connected to the internal circuit voltage Vccin, has a drain-source voltage Vds of 1.1V and a gate-source voltage Vgs of 1V.
If the voltage of the external power supply Vccex is 1.5V in the self-refresh mode, the drain-source voltage Vds of the n-channel MOS transistor Tr9 is 0.1V and the gate-source voltage Vgs is 1V.
Referring to FIG. 3, the transistor Tr9 operates in a saturated range during the normal operation mode and operates in a linear range during the self-refresh mode. Thus, the varying amount W2 of the drain current Ids related to the gate-source voltage Vgs during the normal operation mode is greater compared to the varying amount W1 of the drain current Ids in the self-refresh mode. Thus, the differential amplifier 2 responds slowly to changes in the voltage of the internal circuit voltage Vccin.
As a result, the differential amplifier 2 may not be able to follow a voltage decrease of the internal circuit voltage Vccin. This may result in deficient refreshing or may cause the entire device to stop functioning.
To prevent such deficiency, the transistor Tr2, which is activated during the self-refresh mode, may be enlarged to inhibit a decrease in the voltage of the internal circuit voltage Vccin. However, this would result in a drastic enlargement of the device chip and increase the cost of the device.
FIG. 4 is a schematic circuit diagram of a second prior art example of a DRAM internal power supply generation circuit 60. In the second prior art example, a p-channel MOS transistor Tr3 is activated based on an output signal of a differential amplifier 2 in a normal operation mode. The channel resistance of the transistor Tr3 decreases the voltage of an external power supply Vccex. The decreased voltage (voltage of an internal circuit voltage Vccin) is supplied to an internal circuit 3.
During a self-refresh mode, a p-channel MOS transistor Tr4 is inactivated based on a high detection signal LLD, which is provided from a self-refresh detection circuit 4. In this state, the supply of power to the differential amplifier 2 is stopped to inactivate the differential amplifier 2.
The high detection signal LLD activates an n-channel MOS transistor Tr5 and connects the gate of the transistor Tr3 to a power supply Vss (ground). This activates the transistor Tr3 and supplies the internal circuit 3 with the voltage of the external power supply Vccex (the voltage of the internal circuit voltage Vccin), which is 1.5V, via the transistor Tr3.
In the second prior art example, the transistor Tr3 is used in both normal operation and self-refresh modes. During the normal operation mode, if the transistor Tr3 is unnecessarily large, the tailing characteristic of the transistor Tr3 may excessively increase the voltage of the internal circuit voltage Vccin. Further, the power consumption at the internal circuit voltage Vccin may increase. If the transistor Tr3 is designed so that its size is optimal during the normal operation mode, the current supply capacity of the transistor Tr3 may be insufficient during the self-refresh mode thereby causing a refreshing deficiency.
FIG. 5 is a schematic circuit diagram of a third prior art example of a DRAM internal power supply generation circuit 70. The internal power supply generation circuit 70 includes a first reference voltage generation circuit 5a, which generates a reference voltage Vref1, and a second reference voltage generation circuit 5b, which generates a reference voltage Vref2. The reference voltage Vref2 is lower than the reference voltage Vref1 and functions as a criterion for low voltage operation. The reference voltage Vref1 is supplied to a first differential amplifier 6a, and the reference voltage Vref2 is supplied to a second differential amplifier 6b. 
In the normal operation mode, the voltage of the external power supply Vccex is higher than the reference voltage Vref2. Thus, the output signal of the second differential amplifier 6b is low, and the output signal LLD1 of a NAND circuit 7 is high. This activates an n-channel MOS transistor Tr6 and the first differential amplifier 6a and inactivates a p-channel MOS transistor Tr8.
The p-channel MOS transistor Tr7 is activated based on the first differential amplifier 6a. The channel resistance of the transistor Tr7 decreases the voltage of the external power supply Vccex. The decreased voltage is provided to the internal circuit 3.
In the self-refresh mode, the voltage of the external power supply Vccex decreases to a value lower than the reference voltage Vref2. Thus, the output signal of the second differential amplifier 6b goes high. As a result, the output signal LLD1 of the NAND circuit 7 goes low, the transistor Tr6 is inactivated, and the first differential amplifier 6a is inactivated. The NAND output signal LLD1 activates the transistor Tr8, and the voltage of the external power supply Vccex, which is 1.5V, is supplied to the internal circuit 3.
In the third prior art example, power is supplied to the internal circuit 3 based on the operation of the transistor Tr8. Thus, an enlargement of the transistor Tr8 increases the chip size of the semiconductor memory device.
It is an object of the present invention to provide an internal power supply circuit of a semiconductor memory device that supplies voltage for performing refresh operations without enlarging the chip size of the semiconductor memory device.
To achieve the above object, the present invention provides a power supply circuit for supplying an internal circuit of a semiconductor memory device with power from an external power supply. The power supply circuit includes a first power supply circuit connected to the external power supply and the internal circuit to generate a step down voltage by decreasing a first voltage on the external power supply and to supply the internal circuit with the step down voltage when the semiconductor memory device is in a normal operation mode. A second power supply circuit is connected to the external power supply and the internal circuit to supply the internal circuit with a second voltage on the external power supply when the semiconductor memory device is in a self-refresh mode. A detection circuit is connected to the external power supply and the first and second power supply circuits to detect entry to the self-refresh mode and a voltage level of the external power supply and to generate a detection signal based on the detection of the entry and the voltage level. The first power supply circuit receives the second voltage from the external power supply during the self-refresh mode, and the first and second power supply circuits supply the internal circuit with the second voltage based on the detection signal during the self-refresh mode.
A further perspective of the present invention is a method for supplying an internal circuit of a semiconductor memory device with power from an external power supply. The semiconductor memory device includes a first power supply circuit connected to the external power supply and the internal circuit to generate a step down voltage by decreasing a first voltage on the external power supply and to supply the internal circuit with the step down voltage when the semiconductor memory device is in a normal operation mode. A second power supply circuit is connected to the external power supply and the internal circuit to supply the internal circuit with a second voltage on the external power supply when the semiconductor memory device is in a self-refresh mode. The method includes detecting entry to the self-refresh mode and the supply of the second voltage to the semiconductor memory device, generating a detection signal based on the detection, supplying the internal circuit with the step down voltage from the first power supply circuit based on the detection signal during the normal operation mode, and supplying the internal circuit with the second voltage from the first and second power supply circuits by simultaneously activating the first and second power supply circuits based on the detection signal during the self-refresh mode.
A further perspective of the present invention is a power supply circuit including a first power supply line to receive an external power supply voltage. A second power supply line supplies an internal circuit with an internal power supply voltage. A first transistor is coupled between the first and second power supply lines to supply a step down voltage to the second power supply line in a normal operation mode. A second transistor is coupled between the first and second power supply lines. A detection circuit outputs a detection signal upon a voltage drop on the external power supply voltage during a self refresh mode. The first and second transistor are short-circuited between the first and second power supply lines in response to the detection signal.
Other aspects and advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.